Week in review: design, low power consumption

Design Services Firm Half Five acquired Analog bits, a low-power mixed-signal IP provider. Analog Bits’ portfolio includes precision clock macros, I/Os, SerDes, and sensors for monitoring PVT. It was founded in 1995 and based in Sunnyvale, California. “Analog Bits has a strong track record in developing and delivering high-quality, differentiated mixed-signal IP addressing multiple market segments across various process technologies down to 3nm. This latest acquisition confirms our vision to provide more enabling technologies with differentiated values ​​to all industry players who want access to custom silicon,” said Brandon Cho, CEO and Founder of SemiFive. In addition to fully custom design, SemiFive offers a model-based SoC design platform that uses customizable designs and an IP library to speed up design time and reduce costs. This is the Korean company’s first overseas acquisition. Last month, it announced a $109 million venture capital fundraising. The terms of the contract are not disclosed.

Tools, intellectual property, design
Nvidia has offered a way to connect chiplets with the introduction of NVLink-C2C, an ultra-fast chip-to-chip and chip-to-chip interconnect that will allow custom chips to consistently interconnect to GPUs, CPUs, DPUs, NICs and Enterprise SoC. NVLink-C2C is built on Nvidia’s SERDES and LINK design technology, and is scalable from PCB-level integrations and multi-chip modules to silicon interposers and wafer-level connections. It supports the Arm AMBA Coherent Hub Interface (AMBA CHI) protocol and will also support the Universal Chiplet Interconnect Express (UCIe) standard. The company claims that with advanced packaging, the interconnect would be up to 25 times more power efficient and 90 times more efficient than PCIe Gen 5 on Nvidia chips and enable consistent interconnect bandwidth of 900 gigabytes. per second or more.

Microsoft selected Cadence for its part in the Rapid Assured Microelectronics Prototypes (RAMP) Phase II initiative. The RAMP program is a defense department (DoD) to advance secure design methods in microelectronics. “Cadence’s participation in the RAMP program brings performance-optimized streams for DoD use on Microsoft Azure,” said Mujtaba Hamid, general manager, Silicon, Modeling and Simulation, Microsoft. “With this, we have established a more comprehensive EDA design environment for the development of advanced microelectronics to facilitate the delivery of new aerospace and defense applications in a safe and efficient manner.”

Cadences digital solution on Amazon Web Services (AWS) has been qualified by GlobalFoundries for its 22FDX platform. Xenergic noted that he used the Cadence Cloud Passport with the full digital stream and the Tensilica Fusion F1 DSP on the GF 22FDX platform to record a low-power memory test chip for the first time.

Vesta used Ansys SCADE Model-Based Software Development Environment to implement wind turbine controllers with more built-in safety capabilities to optimize power performance and prevent component damage across the full range of wind conditions.

Strategic Enterprises McLarenbusiness accelerator and investment company, founded Atlas Silicona new custom ASIC design company.

Electrical appliances
Infineon launched a new family of 650 V silicon carbide (SiC) MOSFETs that aims to offer improved switching behavior at higher currents and reverse recovery charging (Q rr) and drain-source charging (Q oss) 80% lower than the silicon reference. Available in a compact 7-pin D 2PAK SMD package with .XT interconnect technology, they target high power applications including servers, telecommunications, industrial SMPS, EV fast charging, motor drives, solar energy systems, energy storage and battery formation.

Infineon launched a new EiceDRIVER 2EDN product family consisting of rugged 4A/5A dual channel low-side gate driver ICs. They aim to provide better undervoltage lockout (UVLO) filter time, wake-up faster from UVLO off state and more than twice as fast UVLO reaction from startup and burst mode for fast power MOSFETs as well as wide bandgap switching devices.

Microchip technology introduces 3.3 kV SiC MOSFETs with 25 mOhm RDS(on) and Schottky Barrier Diodes (SBD) with 90 amp current rating. They are available in chip or package form and target electrified transport, renewable energy, aerospace and industrial applications.

Built-in diodes added a new series of low dropout (LDO) voltage regulators. The devices have an input voltage range of 5V to 60V, allowing them to be connected to 5V, 9V, 12V, 24V and 48V rails. They have a quiescent current of 2µA and a power supply rejection ratio (PSRR) of 70dB at 1kHz, as well as fast line/load transient response to help smooth out sudden changes in input voltage and current dump.

Data center, HPC, quantum
AMD introduces a data center processor using 3D matrix stacking. Company claims 3rd Gen AMD EPYC processors with 3D V-Cache technology deliver up to 66% performance improvement on a variety of targeted technical computing workloads such as Computational Fluid Dynamics (CFD) , finite element analysis (FEA), EDA and structure. analysis against comparable non-stacked 3rd Gen AMD EPYC processors. In particular, AMD noted that the 16-core EPYC 7373X processor can deliver up to 66% faster simulations on Synopsys VCS compared to the EPYC 73F3 processor. 3D V-Cache technology bonds the AMD Zen 3 core to the cache module, increasing the amount of L3 while minimizing latency and increasing throughput.

Ansys upgrades its Ansys Cloud to offer access to AMD EPYC 7003 series processors with AMD 3D V-Cache on Microsoft Azure HBv3 virtual machines. Azure said early tests showed up to 80% improvement in large-scale CFD simulations and up to 50% improvement in explicit FEA crash tests.

Nvidia uncorked a Arms Neoverse-based discrete data center processor designed for AI infrastructure and high-performance computing. The Nvidia Grace CPU superchip comprises two CPU chips cohesively connected on the NVLink-C2C chip-to-chip interconnect. It features 144 Arm cores, an LPDDR5x memory subsystem, and 1 TB/s of memory bandwidth.

Nvidia also launched its latest GPU Hopper architecture for data center AI applications. Key to the architecture is the Transformer Engine deep learning model, designed to accelerate the training of AI models. According to the company, “Hopper Tensor Cores have the ability to apply mixed FP8 and FP16 accuracies to dramatically speed up AI calculations for processors. Hopper also triples the FLOPS for TF32, FP64, FP16 and INT8 accuracies compared to the previous generation. The first GPU based on it, the Nvidia H100, is built on a TSMC 4N process. It supports PCIe Gen5 and HBM3, allowing 3TB/s of memory bandwidth. It also includes many features for secure partitioning and confidential computing.

ECA collaborates with a startup C12 quantum electronics produce multi-qubit chips based on wafer-scale carbon nanotubes. The two partners claim to have demonstrated their ability to manufacture in volume basic components to calibrate, control and read qubits, using standard manufacturing processes. “Quantum technology holds great promise for next-generation computing, but still faces significant development challenges for fabricating qubit chips. Combining well-established CMOS technologies with C12’s original approach using carbon nanotubes could accelerate progress towards commercializing quantum computing and manufacturing these chips at scale,” said Sébastien Dauvé, CEO of CEA. -Leti. The collaboration will also investigate the integration of materials to optimize the properties of qubits hosted in carbon nanotubes and will continue work on the design and fabrication of multi-qubit chips. A final full prototype is expected in 2024.

Abdul J. Gaspar